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https://github.com/weiju/amiga-stuff
synced 2025-12-08 14:58:33 +00:00
added more instructions to disassembler
This commit is contained in:
Wei-ju Wu
+108
-27
@@ -13,19 +13,43 @@ ADDR_MODES_EXT = {
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OPCODE_CATEGORIES = {
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'0000': 'bitops_movep_imm', '0001': 'move.b', '0010': 'move.l', '0011': 'move.w',
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'0100': 'misc', '1101': 'add_addx'
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'0100': 'misc', '1001': 'sub_subx',
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'0110': 'bcc_bsr_bra', '0111': 'moveq',
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'1101': 'add_addx'
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}
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ADD_OPMODES = {
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'000': ('b', 'ea+dn->dn'), '001': ('w', 'ea+dn->dn'),'010': ('l', 'ea+dn->dn'),
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'100': ('b', 'dn+ea->ea'), '101': ('w', 'dn+ea->ea'),'110': ('l', 'dn+ea->ea')
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ADD_SUB_OPMODES = {
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'000': ('b', 'ea,dn->dn'), '001': ('w', 'ea,dn->dn'),'010': ('l', 'ea,dn->dn'),
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'100': ('b', 'dn,ea->ea'), '101': ('w', 'dn,ea->ea'),'110': ('l', 'dn,ea->ea')
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}
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SIZES = ['b', 'w', 'l']
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CONDITION_CODES = [
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't', 'f', 'hi', 'ls',
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'cc', 'cs', 'ne', 'eq',
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'vc', 'vs', 'pl', 'mi',
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'ge', 'lt', 'gt', 'le'
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]
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def is_move(category):
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return category in {'move.b', 'move.w', 'move.l'}
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def next_word(size, data, data_offset):
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if size == 'L':
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value = struct.unpack('>i', data[data_offset:data_offset+4])[0]
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added = 4
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elif size == 'W':
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data[data_offset:data_offset+2]
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value = struct.unpack('>h', data[data_offset:data_offset+2])[0]
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added = 2
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else:
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raise Exception('unsupported size: ', size)
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return (value, added)
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def operand(size, mode_bits, reg_bits, data, offset):
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result = ""
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added = 0
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@@ -36,17 +60,20 @@ def operand(size, mode_bits, reg_bits, data, offset):
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mode = ADDR_MODES_EXT[reg_bits]
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regnum = int(reg_bits, 2)
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if mode == '#<data>':
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data_offset = offset + 2
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if size == 'L':
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imm_value = struct.unpack('>i', data[data_offset:data_offset+4])[0]
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added += 4
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elif size == 'W':
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data[data_offset:data_offset+2]
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imm_value = struct.unpack('>h', data[data_offset:data_offset+2])[0]
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added += 2
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else:
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raise Exception('unsupported size: ', size)
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imm_value, added = next_word(size, data, offset + 2)
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result = "#%d" % imm_value
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elif mode in {'(xxx).L', '(xxx).W'}: # absolute
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addr, added = next_word(mode[-1], data, offset + 2)
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result = "%d.%s" % (addr, mode[-1])
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elif mode == '(d16,PC)':
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disp16, added = next_word('W', data, offset + 2)
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result = "%d(PC)" % disp16
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else:
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raise Exception("unsupported ext mode: '%s'" % mode)
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elif mode == '(d16,An)':
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regnum = int(reg_bits, 2)
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disp16, added = next_word('W', data, offset + 2)
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result = "%d(A%d)" % (disp16, regnum)
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else:
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regnum = int(reg_bits, 2)
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result = mode.replace('n', str(regnum))
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@@ -67,43 +94,97 @@ def disassemble_move(bits, data, offset):
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return ((category, src_op, dst_op), total_added)
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def disassemble_add(bits, data, offset):
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def disassemble_add_sub(name, bits, data, offset):
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total_added = 0
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reg = "D%d" % int(bits[4:7], 2)
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size, operation = ADD_OPMODES[bits[7:10]]
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size, operation = ADD_SUB_OPMODES[bits[7:10]]
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ea, added = operand(size, bits[10:13], bits[13:16], data, offset)
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total_added += added
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if operation == 'ea+dn->dn':
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if operation == 'ea,dn->dn':
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src = ea
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dst = reg
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elif operation == 'dn+ea->ea':
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elif operation == 'dn,ea->ea':
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src = reg
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dst = ea
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else:
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raise Exception('Unknown operation for add')
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raise Exception('Unknown operation for %s' % name)
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return (('add.%s' % size, src, dst), total_added)
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return (('%s.%s' % (name, size), src, dst), total_added)
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def disassemble_misc(bits, data, offset):
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if bits == '0100111001110101': # rts
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return (('rts', ), 0)
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elif bits[7:10] == '111': # lea
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regnum = int(bits[4:7], 2)
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ea, added = operand('l', bits[10:13], bits[13:16], data, offset)
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return (('lea', ea, 'A%d' % regnum), added)
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elif bits.startswith('0100111010'): # jsr
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ea, added = operand('l', bits[10:13], bits[13:16], data, offset)
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return (('jsr', ea), added)
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elif bits.startswith('0100111011'): # jmp
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ea, added = operand('l', bits[10:13], bits[13:16], data, offset)
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return (('jmp', ea), added)
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elif bits.startswith('01001010'): # tst.x
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size = SIZES[int(bits[8:10], 2)]
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ea, added = operand('l', bits[10:13], bits[13:16], data, offset)
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return (('test.%s' % size, ea), added)
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else:
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print("unrecognized misc: %s" % bits)
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raise Exception('TODO Misc')
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def disassemble(data, offset):
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bits = "{0:016b}".format(struct.unpack(">H", data[offset:offset+2])[0])
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# first step categorize by looking at bits 15-12
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opcode = bits[0:4]
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category = OPCODE_CATEGORIES[opcode]
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added = 0
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if is_move(category):
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op, added = disassemble_move(bits, data, offset)
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elif category == 'add_addx':
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if bits[7] == 1 and bits[10:12] == '11': # addx
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raise Exception('addx not supported yet')
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elif category in {'add_addx', 'sub_subx'}:
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if bits[7] == 1 and bits[10:12] == '11': # extended
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raise Exception('addx/subx not supported yet')
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else:
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op, added = disassemble_add(bits, data, offset)
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op, added = disassemble_add_sub(category[0:3], bits, data, offset)
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elif category == 'misc':
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op, added = disassemble_misc(bits, data, offset)
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elif category == 'moveq':
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regnum = int(bits[4:7], 2)
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value = int(bits[8:16], 2)
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op = ('moveq', value, 'D%d' % regnum)
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elif category == 'bcc_bsr_bra':
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if bits[0:16] == '01100000': # bra
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raise Exception('BRA TODO')
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elif bits[0:16] == '01100001': # bsr
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raise Exception('BSR TODO')
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else:
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cond = CONDITION_CODES[int(bits[4:8], 2)]
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disp8 = int(bits[8:16], 2)
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if disp8 == 0:
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# 16 bit displacement TODO
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raise Exception('16 bit branch displacement TODO')
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elif disp8 == 255:
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# 16 bit displacement TODO
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raise Exception('16 bit branch displacement TODO')
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if disp8 >= 128:
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raise Exception('wrong value for signed displacement: %d', disp8)
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return (('b%s' % cond, disp8), 2)
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else:
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print("category: ", category)
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print("\nUnknown instruction\nCategory: ", category, " Bits: ", bits)
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raise Exception('TODO')
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return (op, 2 + added)
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def print_instruction(address, op):
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opcode, src, dst = op
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print("$%08x:\t%8s %8s, %8s" % (address, opcode, src, dst))
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if len(op) == 3:
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opcode, src, dst = op
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print("$%08x:\t%8s %s,%s" % (address, opcode, src, dst))
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elif len(op) == 2:
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opcode, ea = op
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print("$%08x:\t%8s %s" % (address, opcode, ea))
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elif len(op) == 1:
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print("$%08x:\t%8s" % (address, op[0]))
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else:
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raise Exception("can't print instruction with %d components" % len(op))
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+3
-1
@@ -159,13 +159,15 @@ def parse_hunkfile(hunkfile):
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elif block[0] == 'BSS':
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print("Block %d: '%s' -> %d" % (i, block[0], block[1]))
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elif block[0] == 'CODE':
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print("%d: '%s'" % (i, block[0]))
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print("%d: '%s', size = %d" % (i, block[0], len(block[1])))
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print("----------------------------\n")
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code = block[1]
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offset = 0
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while offset < len(code):
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op, size = disassemble(code, offset)
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print_instruction(offset, op)
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offset += size
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print("\n---------------------------\n")
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else:
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print("Block %d: '%s'" % (i, block[0]))
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