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- The data structure alignment (file I/O buffer) is now configurable

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at compile time. The default used to be 16 bytes, which is appropriate
  for the 68040/68060 but not for the PowerPC, which uses 32 or 128
  bytes per cache line.


git-svn-id: file:///Users/olsen/Code/migration-svn-zu-git/logical-line-staging/clib2/trunk@14787 87f5fb63-7c3d-0410-a384-fd976d0f7a62
This commit is contained in:
Olaf Barthel
2004-12-26 13:14:47 +00:00
parent ad0880d204
commit e77cc97daf
8 changed files with 34 additions and 39 deletions
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10
library/stdio_headers.h
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@ -1,5 +1,5 @@
/*
* $Id: stdio_headers.h,v 1.5 2004-11-28 10:01:26 obarthel Exp $
* $Id: stdio_headers.h,v 1.6 2004-12-26 13:14:47 obarthel Exp $
*
* :ts=4
*
@ -104,6 +104,14 @@
/****************************************************************************/
/* CPU cache line size; used for alignment purposes with some data structures.
This should be determined dynamically rather than preset here. For the
68040/68060 the cache line size is 16 bytes, for the PowerPC G4 it's
32 bytes and 128 bytes (gross!) for the PowerPC G5. */
#define CACHE_LINE_SIZE 32UL
/****************************************************************************/
/* The directory entry type a socket is identified with (in a FileInfoBlock). */
#define ST_SOCKET (31082002)